EE & CS @ UW–Madison · 2028
Rohtak
Patwardhan
I'm a sophomore Electrical Engineering student at UW-Madison, interested in FPGA, RTL, and embedded systems.
Some of the work I've done includes designing and implementing a single-cycle processor with matrix acceleration on an FPGA. I'm currently working with Insight Wisconsin as the hardware co-lead to innovate our system and release an FESv3 board by the end of the semester with UVLO and LC pi-filter integration.
I admire strong technical documentation and seek to reach industry-level standards with my work. I'm actively open to new opportunities, so feel free to reach out at rohtak.pat314@gmail.com.
Outside of engineering, I enjoy lifting, trying different coffee shops, climbing, and listening to a variety of music.
Projects
Engineering Projects
01
RISC-V Single-Cycle CPU
Single-cycle RV32IM processor implementing 47 RV32I and 8 M-extension instructions. Timing optimization raised Fmax from 28 MHz to 49.18 MHz on Cyclone V while cutting resource use ~15×. 100% pass rate across self-checking and directed testbenches.
02
Gemm
Memory-mapped matrix accelerator computing A x B = C for 4x4 systolic matrices on AXI4-Lite interface. 175x kernel speedup design, ~11x end-to-end. Modular and integrated with RV32IM processor for compute efficiency.
03
Multi-Protocol Instrument Bridge
USB CDC bridge for RP2040 using I2C, SPI, UART, and 1-Wire. Turns hardware validation from write-flash-debug loops into terminal commands.
04
Synapse
In progress. An FPGA compute-in-memory project: the weights stay next to the multiply-accumulate instead of being fetched from external memory.
Experience
Work & Research
- Diagrammed CAN cabling around the entire solar car by referencing SolidWorks model
- Designed changes to the voltage protection stage of the PDC_revB in Altium, changing specific resistors and MOSFETs to match Altium values and maintain voltage constraints
- Applied circuit analysis and DMM techniques for the PCBs to check voltage and current values at different pads
- Soldered op-amp post debugging onto the PDC and soldered the STM32
- Leading FESv3 board design, integrating an under-voltage lockout (UVLO) circuit using a comparator and P-channel MOSFET to disable gate drive when input voltage exceeds the Vx threshold (under test)
- Designing LC pi-filters for high-frequency ripple filtering on the +5V and −5V power rails
- Leading a 10+ member hardware team developing electronics for a lower-limb functional FES device
- Teaching foundational circuit analysis, KiCad PCB design, LTspice, manufacturing processes, and PCBA terminology, alongside using a DMM, power supplies, oscilloscopes, and other laboratory equipment for testing
- Designed an overcurrent protection circuit in KiCad with a 50mA limit and max 25ms response time for patients with lower limb muscle conditions
- Simulated upper and lower window comparator thresholds in LTspice and used a pulsing voltage for testing with tuned parameters based off FES devices on the market
- Presented the design at F25 and SP26 design reviews to the team and incorporated feedback from the team, board, and professors
- Worked with teammates to design a BOM database for electronic parts for the semester
- Configured the TI IWR1843 module in mmWave Studio and MATLAB Runtime 8.5.1, setting up ADC, SPI, and verifying compatibility to begin data collection
- Modernized legacy MATLAB post-processing scripts for real-time sound reconstruction by changing serial port references in the script to allow for better port recognition
- Applied signal processing techniques including DFT/FFT, chirps, and spectrogram analysis
- Cloud Closet Startup
Coursework
Skills